Advances in semiconductor processing are leading to smaller dimensions for each electronic function and therefore a greater density of functions on each semiconductor chip. To further exploit the advantages of increased density, such as: greater speed, lower power, improved system reliability, and lower cost individual chips are packaged and interconnected into chip arrays upon a supporting substrate. These arrays perform such functions as memory, processing, optical sensing, or optical display. What the arrays all have in common is the need for precise alignment of the features on each chip to the coordinates of the substrate and/or each other. The need for precision is particularly acute in optical sensor and emitter arrays because the interrelationship of the chips contributes to the electronic output in image-processing applications. The difficulty in aligning semiconductor chips for optical applications is aggravated by chip geometry, which can range from a square of about one mm on a side to more than 25 mm on a side, and to a highly rectangular die with dimensions up to 70 mm and an aspect ratio of up to 20:1.
Prior art methods of assembly rely on various mechanical positioning devices or optical alignment schemes to precisely locate chips in a three-dimensional x,y,z coordinate array together with proper angular orientation. Many of these approaches suffer from the tolerance accumulation from (1) the accuracy of the saw cuts which separate the chips from their wafer, (2) the accuracy of the edges of mechanical templates which hold the chips in an array, and (3) the movement of the chips in the transfer operation to the interconnecting substrate. What is really needed is the alignment of the pattern on each chip to the pattern on the substrate or each other.
A series of advances have been made in the prior art through the use of temporary supports to mechanically align an array of chips. U.S. Pat. No.
4,766,670 (C. Gazdik et al) describes the use of a flexible polyimide film to hold an array of chips which are subsequently bonded, while being attached to the polyimide film, to a rigid substrate which serves as a heat sink. The precision with which an individual chip remains in relationship to other chips in the array is clearly limited by the dimensional stability of the organic polyimide film which changes with temperature and humidity.
In U.S. Pat. No. 4,375,126 (H. Dull, et al) a series of magazines feed plate-shaped chips to locations upon a transfer plate which correspond to the intended locations of the chips on a printed circuit board. In another embodiment a calibration plate is placed between the magazine ends and the transfer plate. The calibration plate has openings corresponding to the shape and location of the chips. It is movable in x and y directions and thereby cooperates with the transfer plate in aligning the array. There are necessary clearances in the openings in the calibration plate to allow chips fed from the magazine ends to enter and to allow these chips to be transferred to the printed board. These clearances limit the precision of locating chips in an array.
U.S. Pat. No. 4,345,371 (M. Ohsawa, et al) teaches the feeding of parts by magazines to cavities formed in the upper surface of a mechanical template. An adhesive is screened upon a printed wiring board at locations corresponding to the part locations. Then the printed wiring board is lowered, adhesive side down, upon the parts which protrude from the cavities in the template. The template-printed wiring board structure is then turned over, the template is lifted away and the adhesive is cured to hold the parts in place. The precision of location is limited by the clearances needed by the parts for entry into and egress of the parts from the cavities in the template. There is also no opportunity to observe the array in the turnover-transfer operation.
In U.S. Pat. No. 4,292,116 (T. Takahashi et al) the temporary support is a vacuum plate which lifts chips from a series of magazines which are arranged in the same spatial relationship as the intended location of the chips on a printed circuit board. The printed circuit board, coated with an adhesive, is moved below the parts which are held against the temporary support by vacuum, and then the board and support are moved together. The adhesive holds the chips to the board. Pressure is applied to release the chips and the support is removed In the Takahashi et al patent the tolerances between the chips in the array can never be better than the location of the magazines to each other. The density with which chips can be arranged is also limited by the wall thicknesses of adjacent magazines rather than by the ability to interconnect the chips.
Another transfer plate is described in U.S. Pat. Nos. 4,070,229 and 3,982,979 (L. J. Hentz et al) in which inverted, truncated pyramid shaped cavities are machined into a plate. Tubular members are centered in each cavity, are adapted to slide vertically within the cavities, and are resiliently supported by a vacuum chamber. Beam leaded semiconductor devices are placed on the ends of the tubular members. They are centered in the cavity as the tubular members are lowered with a vertical oscillatory motion which causes the devices to engage the walls of the cavity intermittently. A substrate coated with an adhesive is placed over the cavities and the tubular members are raised to press the devices against the adhesive. The mechanical tolerances in the edge of the device are added to the tolerances in machining a tapered cavity. The density of the device array is limited by the machinability of the tapered cavities without causing warpage.
U.S. Pat. No. 3,859,723 (G. H. Hamer et al) teaches a method for the simultaneous bonding of an array of flip-chip semiconductor devices by placing each flip-chip in an aperture in a metal template and by holding the chips in place with a high-temperature adhesive tape covering the back of the template. The template is registered over a substrate and thereafter the chips are bonded by soldering or thermocompression bonding. The tolerances between the various chips in the array are dominated by the mechanical tolerances on the edge of the chip and the clearances needed for passage of the chip into and out of the template.
Optical means of chip alignment are also described in the literature. In U.S. Pat. No. 4,675,993 (Y. Harada) a vacuum fastener picks up an electronic component from a tape reel, and an image sensor provides error signals to a numerical controller which positions a printed circuit board below the component. Great precision is achievable with numerical control, but the expense may not be justified in all instances.
U.S. Pat. No. 4,222,036 (T. Troukens) describes a method for positioning components on printed circuit boards using a projection display system to indicate the holes in the printed circuit board for the mounting of particular components. This position-locating aid is intended primarily for hand assembly.
A method of encapsulating coplanar microelectronic components is described in U.S. Pat. No. 3,656,232 (J. F. Hinchey) wherein a transparent mold plate containing gauge marks on its upper surface is coated with a mold release compound or wax which also serves to hold components placed on the mold plate from above. The mold plate rests upon a mirror. An operator views the gauge marks on the upper surface of the mold plate and the component above the mold plate reflected by the mirror at an angle to the vertical line of the chip movement during placement. Interconnection is achieved by casting an insulator around the components on the mold plate, releasing the mold plate, and electrically interconnecting the components. The parallax in viewing the gauge marks and the component above the marks at an angle impedes the rapid and accurate placement of a component in a precision array.
It is desirable to have a method for placing and bonding an array of semiconductor chips which are precisely located with respect to each other in orthogonal x, y, and z axes and also in angular orientation. It is also advantageous to inspect the array before bonding to the ultimate supporting member. Temporary supports for the array in the method should not contribute to inaccuracies in location due to dimensional changes with temperature and humidity. The packing density on the ultimate supporting member should be limited only by the constraints of interconnecting the chips, and not by the placement method.